Careers
AnalogSemi provides our employees with the best working environment that promotes individual career growth combined with healthy work-life balance and a rewarding oppurtunity. Our growth and success demands continous investment at people, hence we consider employees are the biggest asset, we take utmost care of them. We would be happy to speak to you whether you are a professional or a recent graduate. With your goals and our vision, AnalogSemi can provide a promising and brightful career that inspires people to unleash their talent and realize their potential.
JOB OPENINGS
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a)Job Code : AMS-CD01
Designation : Circuit Design Engineer
Experience : 2-4 years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• Design of high performance CMOS Analog and Mixed Signal Circuits.
• Circuit Design, Simulation, Verification & Documentation.
• Adhere to Project Execution Plan & Work Assignment.
• Support senior members of the team in project planning and implementation.
• Mentor and guide junior members of the team.
Required Skillset
• Hands on experience in design of basic analog circuits: Op amps, Comparators, Bandgap, LDOs, Voltage Reference Buffers & Switched capacitor circuits.
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS Process
• Proficiency in using industry standard EDA tools(Spectre, MMSIM, Hspice & Hsim)
• Strong analytical and problem solving skills.
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A.
• Strong fundamentals in MOS device physics and Circuit theory.
• Good team player with excellent communication skills.
b) Job Code : AMS-CD02
Designation : Senior Circuit Design Engineer
Experience : 4-6 years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• To understand Project/Customer requirements and design high performance CMOS Analog and Mixed Signal Circuits.
• Involve in Feasibility Study, Circuit Design, Pre & Post Layout simulations and Documentation.
• Adhere to Project Execution Plan & Work Assignment.
• Active Participation in multiple internal & external customer reviews
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and Independent handling of various Analog and Mixed Signal blocks such as ADC, DAC, PLL, CDR, SerDes, LVDS, HDMI, PMIC, DC-DC Converters and LDOs
• Knowledge of Low Voltage & Low Power CMOS Design Techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/BiCMOS process
• Strong analytical and problem solving skills to ensure project schedules are met
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim)
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A.
• Strong fundamentals in MOS device physics, Circuit theory & Top level integrations
• Good team player with excellent communication skills, interface with layout team
• Must have participated in multiple successful Tape-outs.
• Experience in RF design is a plus
c) Job Code : AMS-CD03
Designation : Team Lead – Circuit Design
Experience : 6+ years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Mentor and Guide Junior & Senior members of the team
Required Skillset
• Deep understanding and Managing projects of complex Analog and Mixed Signal blocks such as ADC, DAC, Integer & Fractional PLL, Ring Oscillator, LC VCO, CDRs, SerDes, HDMI, Serial I/Os, LVDS, PMIC, DC-DC Buck, Boost & Buck-Boost converters and LDO
• Expertise in High Speed, Low Voltage and Low Power CMOS Design Techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/BiCMOS process
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim)
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A.
• Strong fundamentals in MOS device physics, Circuit theory and Top level integration.
• Experience in post silicon evaluation
• Strong technical leadership and people management skills
• Must have multiple tape-outs with silicon success across different processes & foundries
• Experience in RF design is a plus
a)Job Code : AMS-CD01
Designation : Circuit Design Engineer
Experience : 2-4 years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• Design of high performance CMOS Analog and Mixed Signal Circuits.
• Circuit Design, Simulation, Verification & Documentation.
• Adhere to Project Execution Plan & Work Assignment.
• Support senior members of the team in project planning and implementation.
• Mentor and guide junior members of the team.
Required Skillset
• Hands on experience in design of basic analog circuits: Op amps, Comparators, Bandgap, LDOs, Voltage Reference Buffers & Switched capacitor circuits.
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS Process
• Proficiency in using industry standard EDA tools(Spectre, MMSIM, Hspice & Hsim)
• Strong analytical and problem solving skills.
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A.
• Strong fundamentals in MOS device physics and Circuit theory.
• Good team player with excellent communication skills.
b) Job Code : AMS-CD02
Designation : Senior Circuit Design Engineer
Experience : 4-6 years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• To understand Project/Customer requirements and design high performance CMOS Analog and Mixed Signal Circuits.
• Involve in Feasibility Study, Circuit Design, Pre & Post Layout simulations and Documentation.
• Adhere to Project Execution Plan & Work Assignment.
• Active Participation in multiple internal & external customer reviews
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and Independent handling of various Analog and Mixed Signal blocks such as ADC, DAC, PLL, CDR, SerDes, LVDS, HDMI, PMIC, DC-DC Converters and LDOs
• Knowledge of Low Voltage & Low Power CMOS Design Techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/BiCMOS process
• Strong analytical and problem solving skills to ensure project schedules are met
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim)
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A.
• Strong fundamentals in MOS device physics, Circuit theory & Top level integrations
• Good team player with excellent communication skills, interface with layout team
• Must have participated in multiple successful Tape-outs.
• Experience in RF design is a plus
c) Job Code : AMS-CD03
Designation : Team Lead – Circuit Design
Experience : 6+ years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Mentor and Guide Junior & Senior members of the team
Required Skillset
• Deep understanding and Managing projects of complex Analog and Mixed Signal blocks such as ADC, DAC, Integer & Fractional PLL, Ring Oscillator, LC VCO, CDRs, SerDes, HDMI, Serial I/Os, LVDS, PMIC, DC-DC Buck, Boost & Buck-Boost converters and LDO
• Expertise in High Speed, Low Voltage and Low Power CMOS Design Techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/BiCMOS process
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim)
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A.
• Strong fundamentals in MOS device physics, Circuit theory and Top level integration.
• Experience in post silicon evaluation
• Strong technical leadership and people management skills
• Must have multiple tape-outs with silicon success across different processes & foundries
• Experience in RF design is a plus
Press Esc to close
a)Job Code : AMS-LD01
Designation : Layout Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech/ Diploma in Electronics Engineering
Job Description
• Layout design & Verification of high performance Analog & Mixed signal blocks
• Adhere to Project Execution Plan & Work Assignment.
• Support senior members of the team in project planning and implementation.
• Mentor and guide junior members of the team.
Required Skillset
• Hands on experience in Layout design of basic analog blocks such as Op amps, Comparators, Bandgap, LDOs, Voltage Reference Buffers & Switched capacitor circuits.
• Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes like 28nm, 45nm, 65nm etc
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing.
• Debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Should have good knowledge of CMOS process and fabrication
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl and Skill is a plus.
• Good team player with excellent communication skills.
b)Job Code : AMS-LD02
Designation : Senior Layout Design Engineer
Experience : 4-6 years
Qualification : BE/ B.Tech/ ME/ M.Tech Degree in Electronics Engineering
Job Description
• Layout design, Verification, Post-layout fixes and sign-off of high performance of Analog and Mixed Signal blocks
• Should be independently handling the blocks starting from floor-planning till tapeout
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Have good understanding of CMOS process and fabrication
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and Independent handling of various Analog and Mixed Signal blocks such as ADC, DAC, PLL, CDR, SerDes, LVDS, HDMI, PMIC, DC-DC Converters and LDOs
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS Process
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing.
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl and Skill is a plus
• Good team player with excellent communication skills, interfacing with the circuit team
• Must have participated in multiple successful Tape-outs
• Experience in RF design is a plus
c)Job Code : AMS-LD03
Designation : Team Lead – Layout Design
Experience : 6-8 years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
Required Skillset
• Deep understanding and Managing layout projects of complex Analog and Mixed Signal blocks such as ADC, DAC, Integer & Fractional PLL, Ring Oscillator, LC VCO, CDRs, SerDes, HDMI, Serial I/Os, LVDS, PMIC, DC-DC Buck, Boost & Buck-Boost converters and LDO
• Expertise in High Speed, Low Voltage and Low Power CMOS layout design techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS process
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Good knowledge on EMIR and ESD analysis and checks
• Proficiency in using industry standard EDA tools Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) and Apache EMIR Analysis.
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Experience in post silicon evaluation
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Must have multiple tape-outs with silicon success across different processes & foundries
• Experience in RF design is a plus
d)Job Code : AMS-LD04
Designation : Manager – Layout Design
Experience : 9+ years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Support in the business development, strategy planning
Required Skillset
• Managing layout projects of complex Analog and Mixed Signal blocks such as ADC, DAC, Integer & Fractional PLL, Ring Oscillator, LC VCO, CDRs, SerDes, HDMI, Serial I/Os, LVDS, PMIC, DC-DC Buck, Boost & Buck-Boost converters and LDO
• Expertise in High Speed, Low Voltage and Low Power CMOS layout design techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS process
• Knowledge of Library development projects in the technology nodes from 180nm to 14nm
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Good knowledge on EMIR and ESD analysis and checks
• Proficiency in using industry standard EDA tools Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) and Apache EMIR Analysis.
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Experience in RF design is a plus
• Experience in post silicon evaluation
• Strong technical leadership and people management skills
• Must have multiple tape-outs with silicon success across different processes & foundries
a)Job Code : AMS-LD01
Designation : Layout Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech/ Diploma in Electronics Engineering
Job Description
• Layout design & Verification of high performance Analog & Mixed signal blocks
• Adhere to Project Execution Plan & Work Assignment.
• Support senior members of the team in project planning and implementation.
• Mentor and guide junior members of the team.
Required Skillset
• Hands on experience in Layout design of basic analog blocks such as Op amps, Comparators, Bandgap, LDOs, Voltage Reference Buffers & Switched capacitor circuits.
• Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes like 28nm, 45nm, 65nm etc
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing.
• Debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Should have good knowledge of CMOS process and fabrication
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl and Skill is a plus.
• Good team player with excellent communication skills.
b)Job Code : AMS-LD02
Designation : Senior Layout Design Engineer
Experience : 4-6 years
Qualification : BE/ B.Tech/ ME/ M.Tech Degree in Electronics Engineering
Job Description
• Layout design, Verification, Post-layout fixes and sign-off of high performance of Analog and Mixed Signal blocks
• Should be independently handling the blocks starting from floor-planning till tapeout
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Have good understanding of CMOS process and fabrication
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and Independent handling of various Analog and Mixed Signal blocks such as ADC, DAC, PLL, CDR, SerDes, LVDS, HDMI, PMIC, DC-DC Converters and LDOs
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS Process
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing.
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl and Skill is a plus
• Good team player with excellent communication skills, interfacing with the circuit team
• Must have participated in multiple successful Tape-outs
• Experience in RF design is a plus
c)Job Code : AMS-LD03
Designation : Team Lead – Layout Design
Experience : 6-8 years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
Required Skillset
• Deep understanding and Managing layout projects of complex Analog and Mixed Signal blocks such as ADC, DAC, Integer & Fractional PLL, Ring Oscillator, LC VCO, CDRs, SerDes, HDMI, Serial I/Os, LVDS, PMIC, DC-DC Buck, Boost & Buck-Boost converters and LDO
• Expertise in High Speed, Low Voltage and Low Power CMOS layout design techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS process
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Good knowledge on EMIR and ESD analysis and checks
• Proficiency in using industry standard EDA tools Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) and Apache EMIR Analysis.
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Experience in post silicon evaluation
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Must have multiple tape-outs with silicon success across different processes & foundries
• Experience in RF design is a plus
d)Job Code : AMS-LD04
Designation : Manager – Layout Design
Experience : 9+ years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Support in the business development, strategy planning
Required Skillset
• Managing layout projects of complex Analog and Mixed Signal blocks such as ADC, DAC, Integer & Fractional PLL, Ring Oscillator, LC VCO, CDRs, SerDes, HDMI, Serial I/Os, LVDS, PMIC, DC-DC Buck, Boost & Buck-Boost converters and LDO
• Expertise in High Speed, Low Voltage and Low Power CMOS layout design techniques.
• Exposure to technology node from 0.18um to 28nm CMOS/ BiCMOS process
• Knowledge of Library development projects in the technology nodes from 180nm to 14nm
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Good knowledge on EMIR and ESD analysis and checks
• Proficiency in using industry standard EDA tools Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) and Apache EMIR Analysis.
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Experience in RF design is a plus
• Experience in post silicon evaluation
• Strong technical leadership and people management skills
• Must have multiple tape-outs with silicon success across different processes & foundries
Press Esc to close
a)Job Code : LIB-CD01
Designation : Circuit Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech/ ME/M.Tech Degree in Electronics Engineering
Job Description
• Design and Characterisation of high performance, high speed Library cells
• Adhere to project execution plan & Work assignment
• Support senior members of the team in project planning and implementation
• Mentor and guide junior members of the team
Required Skillset
• Hands on experience in design and characterisation of Standard Cells, IOs and Memory
• Exposure to technology node from 0.18um to 14nm CMOS Process
• Proficiency in using industry standard EDA tools(Spectre, MMSIM, Hspice, Hsim, SiliconSmart)
• Strong analytical and problem solving skills
• Knowledge of scripting and modelling languages like Perl, Skill Ocean
• Strong fundamentals in MOS device physics and Circuit theory
• Good team player with excellent communication skills
b)Job Code : LIB-CD02
Designation : Senior Circuit Design Engineer
Experience : 4-6 years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• To understand Project / Customer requirements and design high performance Library cells
• Involve in Feasibility Study, Circuit Design, Pre/ Post Layout simulations and Documentation
• Adhere to Project Execution Plan & Work Assignment.
• Active Participation in multiple internal & external customer reviews
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and independently handling of multiple families of Standard cells, IOs & memory compiler library
• Knowledge of Low Voltage & Low Power CMOS Design Techniques
• Exposure to technology node from 0.18um to 14nm CMOS process
• Strong analytical and problem solving skills to ensure project schedules are met
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim, SiliconSmart)
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Knowledge of ESD devices design and implementation is a plus
• Strong fundamentals in MOS device physics, Circuit theory
• Good team player with excellent communication skills, interface with layout team
• Must have participated in successful release of multiple libraries across process nodes
c)Job Code : LIB-CD03
Designation : Team Lead – Circuit Design
Experience : 6+ years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Mentor and guide junior & senior members of the team
Required Skillset
• Deep understanding and Managing projects of multiple high speed, high performance libraries of Standard cells, IOs and Memory compiler
• Expertise in High Speed, Low Voltage and Low Power CMOS Design Techniques
• Exposure to technology node from 0.18um to 14nm CMOS process
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim, SiliconSmart)
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A
• Knowledge of ESD devices design and implementation is a plus
• Strong fundamentals in MOS device physics, Circuit theory
• Experience in post silicon evaluation and re-characterisation
• Strong technical leadership and people management skills
• Must have participated in successful release of multiple libraries across process nodes and foundries
a)Job Code : LIB-CD01
Designation : Circuit Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech/ ME/M.Tech Degree in Electronics Engineering
Job Description
• Design and Characterisation of high performance, high speed Library cells
• Adhere to project execution plan & Work assignment
• Support senior members of the team in project planning and implementation
• Mentor and guide junior members of the team
Required Skillset
• Hands on experience in design and characterisation of Standard Cells, IOs and Memory
• Exposure to technology node from 0.18um to 14nm CMOS Process
• Proficiency in using industry standard EDA tools(Spectre, MMSIM, Hspice, Hsim, SiliconSmart)
• Strong analytical and problem solving skills
• Knowledge of scripting and modelling languages like Perl, Skill Ocean
• Strong fundamentals in MOS device physics and Circuit theory
• Good team player with excellent communication skills
b)Job Code : LIB-CD02
Designation : Senior Circuit Design Engineer
Experience : 4-6 years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• To understand Project / Customer requirements and design high performance Library cells
• Involve in Feasibility Study, Circuit Design, Pre/ Post Layout simulations and Documentation
• Adhere to Project Execution Plan & Work Assignment.
• Active Participation in multiple internal & external customer reviews
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and independently handling of multiple families of Standard cells, IOs & memory compiler library
• Knowledge of Low Voltage & Low Power CMOS Design Techniques
• Exposure to technology node from 0.18um to 14nm CMOS process
• Strong analytical and problem solving skills to ensure project schedules are met
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim, SiliconSmart)
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Knowledge of ESD devices design and implementation is a plus
• Strong fundamentals in MOS device physics, Circuit theory
• Good team player with excellent communication skills, interface with layout team
• Must have participated in successful release of multiple libraries across process nodes
c)Job Code : LIB-CD03
Designation : Team Lead – Circuit Design
Experience : 6+ years
Qualification : BE/B.Tech/ME/M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Mentor and guide junior & senior members of the team
Required Skillset
• Deep understanding and Managing projects of multiple high speed, high performance libraries of Standard cells, IOs and Memory compiler
• Expertise in High Speed, Low Voltage and Low Power CMOS Design Techniques
• Exposure to technology node from 0.18um to 14nm CMOS process
• Proficiency in using industry standard EDA tools (Spectre, MMSIM, Hspice & Hsim, SiliconSmart)
• Knowledge of scripting and modelling languages like Perl, Ocean, Verilog-A
• Knowledge of ESD devices design and implementation is a plus
• Strong fundamentals in MOS device physics, Circuit theory
• Experience in post silicon evaluation and re-characterisation
• Strong technical leadership and people management skills
• Must have participated in successful release of multiple libraries across process nodes and foundries
Press Esc to close
a)Job Code : LIB-LD01
Designation : Layout Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech/ Diploma in Electronics Engineering
Job Description
• Layout design & Verification of high performance, High speed library cells
• Adhere to Project Execution Plan & Work Assignment
• Support senior members of the team in project planning and implementation
• Mentor and guide junior members of the team
Required Skillset
• Hands on experience in Layout design of Standard Cells, IOs and Memory
• Good Understanding of deep sub-micron layout techniques and issues in CMOS technology nodes from 0.18um to 14nm designs
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing
• Debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc
• Should have good knowledge of CMOS process and fabrication
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl, Skill , Ocean
• Good team player with excellent communication skills
b)Job Code : LIB-LD02
Designation : Senior Layout Design Engineer
Experience : 4-6 years
Qualification : BE/ B.Tech/ ME/ M.Tech Degree in Electronics Engineering
Job Description
• Layout design, Verification, Post-layout fixes and sign-off of high performance libraries
• Should be independently handling the modules starting from floor-planning till tapeout
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and independently handling of multiple families of Standard cells, IOs & memory compiler library
• Exposure to technology node from 0.18um to 14nm CMOS Process
• Have good understanding of CMOS process and fabrication
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc
• Knowledge of ESD devices design and implementation is a plus
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl, Skill & Ocean is a plus
• Good team player with excellent communication skills, interfacing with the circuit team
• Must have participated in successful release of multiple libraries across process nodes
c)Job Code : LIB-LD03
Designation : Team Lead – Layout Design
Experience : 6+ years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final release
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Mentor and guide junior & senior members of the team
Required Skillset
• Deep understanding and Managing projects of multiple high speed, high performance libraries of Standard cells, IOs and Memory compiler
• Expertise in High Speed, Low Voltage and Low Power CMOS layout design techniques from 0.18um to 14nm CMOS process
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc
• Knowledge of ESD devices design and implementation is a plus
• Proficiency in using industry standard EDA tools Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) and Apache EMIR Analysis
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Experience in post silicon evaluation
• Must have participated in successful release of multiple libraries across process nodes and foundries
• Strong technical leadership and people management skills
a)Job Code : LIB-LD01
Designation : Layout Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech/ Diploma in Electronics Engineering
Job Description
• Layout design & Verification of high performance, High speed library cells
• Adhere to Project Execution Plan & Work Assignment
• Support senior members of the team in project planning and implementation
• Mentor and guide junior members of the team
Required Skillset
• Hands on experience in Layout design of Standard Cells, IOs and Memory
• Good Understanding of deep sub-micron layout techniques and issues in CMOS technology nodes from 0.18um to 14nm designs
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing
• Debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc
• Should have good knowledge of CMOS process and fabrication
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl, Skill , Ocean
• Good team player with excellent communication skills
b)Job Code : LIB-LD02
Designation : Senior Layout Design Engineer
Experience : 4-6 years
Qualification : BE/ B.Tech/ ME/ M.Tech Degree in Electronics Engineering
Job Description
• Layout design, Verification, Post-layout fixes and sign-off of high performance libraries
• Should be independently handling the modules starting from floor-planning till tapeout
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Mentor and guide the team of Design Engineers
Required Skillset
• Deep understanding and independently handling of multiple families of Standard cells, IOs & memory compiler library
• Exposure to technology node from 0.18um to 14nm CMOS Process
• Have good understanding of CMOS process and fabrication
• Expertise in critical layout design techniques such as Matching, Signal flow, Clock Routing, Shielding, Resistance & Capacitance reduction, Bias and Power routing
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc
• Knowledge of ESD devices design and implementation is a plus
• Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC)
• Knowledge of scripting languages such as Perl, Skill & Ocean is a plus
• Good team player with excellent communication skills, interfacing with the circuit team
• Must have participated in successful release of multiple libraries across process nodes
c)Job Code : LIB-LD03
Designation : Team Lead – Layout Design
Experience : 6+ years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final release
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Mentor and guide junior & senior members of the team
Required Skillset
• Deep understanding and Managing projects of multiple high speed, high performance libraries of Standard cells, IOs and Memory compiler
• Expertise in High Speed, Low Voltage and Low Power CMOS layout design techniques from 0.18um to 14nm CMOS process
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc
• Knowledge of ESD devices design and implementation is a plus
• Proficiency in using industry standard EDA tools Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) and Apache EMIR Analysis
• Knowledge of scripting and modelling languages like Perl, Skill, Ocean
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Experience in post silicon evaluation
• Must have participated in successful release of multiple libraries across process nodes and foundries
• Strong technical leadership and people management skills
Press Esc to close
a)Job Code : ASIC/SoC-PD01
Designation : Physical Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech in Electronics Engineering
Job Description
• Physical Design & Verification of blocks with multi-voltage and multi-clock domains
• Understanding timing constraints and the need for various timing corners for sign-off
• Implementing full and metal ECOs very quickly
• Adhere to Project Execution Plan & Work Assignment.
• Support senior members of the team in project planning and implementation.
• Mentor and Guide Junior members of the team.
Required Skillset
• Strong background of logic design fundamentals and ASIC design experience with P&R tools
• Block level Floor planning, power analysis, Clock Tree Synthesis, Place & Route , timing and Signal Integrity closure, DFT, STA, Physical verification and extraction
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Debugging skills in Timing closure & Physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Should have good knowledge of CMOS process and fabrication
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Candidates with exposure to Synthesis flow is a plus.
• Good team player with excellent communication skills.
b)Job Code : ASIC/SoC-PD02
Designation : Senior Physical Design Engineer
Experience : 4-6 years
Qualification : BE/ B.Tech/ ME/ M.Tech Degree in Electronics Engineering
Job Description
• Physical Design & Verification of blocks & full chip with multi-voltage and multi-clock domains
• Understanding timing constraints and the need for various timing corners for sign-off
• Implementing full and metal ECOs very quickly
• Should be independently handling the blocks & full chip starting from floor-planning till tapeout
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Mentor and guide the team of Design Engineers
Required Skillset
• Strong background of logic design fundamentals and ASIC design experience with P&R tools
• Block and chip level Floor planning, power analysis, Clock Tree Synthesis, Place & Route , timing and Signal Integrity closure, DFT, STA, full chip physical verification and extraction
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Exposure to technology node from 65nm to 14nm CMOS Process
• Good debugging skills in Power Analysis, Timing Closure & all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Good team player with excellent communication skills, interfacing with the front end RTL / Verification team
• Must have participated in multiple successful Tape-outs
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Candidates with exposure to Synthesis flow is a plus.
• Good team player with excellent communication skills.
c)Job Code : ASIC/SoC-PD03
Designation : Team Lead – Physical Design
Experience : 6-8 years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed design requirements, architecture and micro-architecture development, conduct design reviews
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
Required Skillset
• Deep understanding and Managing physical design projects of complex digital / Mixed signal ASICs / SoCs implementation
• Expertise in High Speed, Low Voltage and Low Power physical design techniques.
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good debugging skills in Power Analysis, Timing Closure
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Must have participated in multiple successful Tape-outs
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Good team player with excellent communication skills, interfacing with the front end RTL / Verification team
• Must have multiple tape-outs with silicon success across different processes & foundries
• Full understanding of hierarchical design planning (top down and bottom up) and integration
d)Job Code : ASIC/SoC-PD04
Designation : Manager – Physical Design
Experience : 9+ years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed design requirements, architecture and micro-architecture development, conduct design reviews
• Envision, build and lead a team for successful project execution
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
• Support in the business development, strategy planning
Required Skillset
• Deep understanding and Managing physical design projects of complex digital / Mixed signal ASICs / SoCs implementation
• Expertise in High Speed, Low Voltage and Low Power physical design techniques.
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Good debugging skills in Power Analysis, Timing Closure
• Debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Full understanding of hierarchical design planning (top down and bottom up) and integration • Experience in post silicon evaluation is plus
• Strong technical leadership and people management skills
• Must have multiple tape-outs with silicon success across different processes & foundries
a)Job Code : ASIC/SoC-PD01
Designation : Physical Design Engineer
Experience : 2-4 years
Qualification : BE/ B.Tech in Electronics Engineering
Job Description
• Physical Design & Verification of blocks with multi-voltage and multi-clock domains
• Understanding timing constraints and the need for various timing corners for sign-off
• Implementing full and metal ECOs very quickly
• Adhere to Project Execution Plan & Work Assignment.
• Support senior members of the team in project planning and implementation.
• Mentor and Guide Junior members of the team.
Required Skillset
• Strong background of logic design fundamentals and ASIC design experience with P&R tools
• Block level Floor planning, power analysis, Clock Tree Synthesis, Place & Route , timing and Signal Integrity closure, DFT, STA, Physical verification and extraction
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Debugging skills in Timing closure & Physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Should have good knowledge of CMOS process and fabrication
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Candidates with exposure to Synthesis flow is a plus.
• Good team player with excellent communication skills.
b)Job Code : ASIC/SoC-PD02
Designation : Senior Physical Design Engineer
Experience : 4-6 years
Qualification : BE/ B.Tech/ ME/ M.Tech Degree in Electronics Engineering
Job Description
• Physical Design & Verification of blocks & full chip with multi-voltage and multi-clock domains
• Understanding timing constraints and the need for various timing corners for sign-off
• Implementing full and metal ECOs very quickly
• Should be independently handling the blocks & full chip starting from floor-planning till tapeout
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Mentor and guide the team of Design Engineers
Required Skillset
• Strong background of logic design fundamentals and ASIC design experience with P&R tools
• Block and chip level Floor planning, power analysis, Clock Tree Synthesis, Place & Route , timing and Signal Integrity closure, DFT, STA, full chip physical verification and extraction
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Exposure to technology node from 65nm to 14nm CMOS Process
• Good debugging skills in Power Analysis, Timing Closure & all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Good team player with excellent communication skills, interfacing with the front end RTL / Verification team
• Must have participated in multiple successful Tape-outs
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Candidates with exposure to Synthesis flow is a plus.
• Good team player with excellent communication skills.
c)Job Code : ASIC/SoC-PD03
Designation : Team Lead – Physical Design
Experience : 6-8 years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed design requirements, architecture and micro-architecture development, conduct design reviews
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
Required Skillset
• Deep understanding and Managing physical design projects of complex digital / Mixed signal ASICs / SoCs implementation
• Expertise in High Speed, Low Voltage and Low Power physical design techniques.
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good debugging skills in Power Analysis, Timing Closure
• Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Must have participated in multiple successful Tape-outs
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Good team player with excellent communication skills, interfacing with the front end RTL / Verification team
• Must have multiple tape-outs with silicon success across different processes & foundries
• Full understanding of hierarchical design planning (top down and bottom up) and integration
d)Job Code : ASIC/SoC-PD04
Designation : Manager – Physical Design
Experience : 9+ years
Qualification : BE/B.Tech / ME/ M.Tech Degree in Electronics Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed design requirements, architecture and micro-architecture development, conduct design reviews
• Envision, build and lead a team for successful project execution
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
• Support in the business development, strategy planning
Required Skillset
• Deep understanding and Managing physical design projects of complex digital / Mixed signal ASICs / SoCs implementation
• Expertise in High Speed, Low Voltage and Low Power physical design techniques.
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good Understanding on signal flow, Clock Routing, Shielding, Load Cap reduction techniques, power & ground structure, Bias signal routing.
• Good Understanding of deep sub-micron PD techniques and issues in CMOS process technology nodes like 14nm, 28nm, 45nm, 65nm etc
• Good debugging skills in Power Analysis, Timing Closure
• Debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
• Proficiency in using industry standard P&R EDA tools like Cadence SoC Encounter, Synopsys IC Compiler, Mentor Graphics, Apache Redhawk
• Full understanding of hierarchical design planning (top down and bottom up) and integration • Experience in post silicon evaluation is plus
• Strong technical leadership and people management skills
• Must have multiple tape-outs with silicon success across different processes & foundries
Press Esc to close
a)Job Code : ASIC/SoC-VER01
Designation : Verification Engineer
Experience : 2-4 years
Qualification : BE/B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Responsible for implementing the verification models, integrating the verification environments at block / module level
• Develop scripts based utilities and support verification activities
• Adhere to Project Execution Plan & Work Assignment
• Support senior members of the team in project planning and implementation
• Mentor and Guide Junior members of the team
Required Skillset
• Develop block level test benches and verification environments using Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and/or other verification languages as appropriate.
• Should have participated in successful completion of multiple block level verification
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
• Must have good understanding of embedded processor based SoC architecture
• Good understanding of ARM processor architecture is plus.
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, and Ethernet etc
• Good team player with excellent communication skills.
b)Job Code : ASIC/SoC-VER02
Designation : Senior Verification Engineer
Experience : 4-6 years
Qualification : B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Responsible for Defining & Implementing the ASIC / SoC Verification models, integrating the verification environments, both at block level & full chip level
• Develop scripts based utilities and support verification activities
• Senior Verification engineer needs to closely work with ASIC/SoC architects in defining and developing the verification environment
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Mentor and guide the team of Design Engineers
Required Skillset
• Develop block and system-level test benches and verification environments using Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and/or other verification languages as appropriate.
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
• Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification.
• Good understanding of ARM processor architecture is plus.
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good team player with excellent communication skills, interfacing with the RTL Design team / Architects
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, and Ethernet etc
• Must have participated in multiple successful releases of verification modules
c)Job Code : ASIC/SoC-VER03
Designation : Team Lead – Verification
Experience : 6-10 years
Qualification : B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed Verification requirements, Environment, Test Bench development and conduct design reviews
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
Required Skillset
• Proven experience of the design verification methodologies such as Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and assertion based coverage driven verification (code & functional coverage), constraint random test generation
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
• Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC
• Must have good understanding about different modelling schemes – TLM, behavior/abstract level, cycle accurate, etc
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification.
• Good understanding of ARM & other processor architecture
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, DDR2/3 controller, SATA controller and NAND flash controller and Ethernet etc
• Must have participated in multiple successful releases of verification deliverables
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Good team player with excellent communication skills, interfacing with the RTL Design team / Architects
d)Job Code : ASIC/SoC-VER04
Designation : Manager – Verification
Experience : 10+ years
Qualification : B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed Verification requirements, Environment, Test Bench development and conduct design reviews
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
• Support in the business development, strategy planning
Required Skillset
• Proven experience of the design verification methodologies such as Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and assertion based coverage driven verification (code & functional coverage), constraint random test generation
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage for complex ASIC / SoC designs
• Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC
• Must have good understanding about different modelling schemes – TLM, behavior/abstract level, cycle accurate, etc
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification.
• Good understanding of ARM & other processor architecture
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, DDR2/3 controller, SATA controller and NAND flash controller and Ethernet etc
• Must have participated in multiple successful releases of verification modules
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Good team player with excellent communication skills
• Strong technical leadership and people management skills
a)Job Code : ASIC/SoC-VER01
Designation : Verification Engineer
Experience : 2-4 years
Qualification : BE/B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Responsible for implementing the verification models, integrating the verification environments at block / module level
• Develop scripts based utilities and support verification activities
• Adhere to Project Execution Plan & Work Assignment
• Support senior members of the team in project planning and implementation
• Mentor and Guide Junior members of the team
Required Skillset
• Develop block level test benches and verification environments using Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and/or other verification languages as appropriate.
• Should have participated in successful completion of multiple block level verification
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
• Must have good understanding of embedded processor based SoC architecture
• Good understanding of ARM processor architecture is plus.
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, and Ethernet etc
• Good team player with excellent communication skills.
b)Job Code : ASIC/SoC-VER02
Designation : Senior Verification Engineer
Experience : 4-6 years
Qualification : B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Responsible for Defining & Implementing the ASIC / SoC Verification models, integrating the verification environments, both at block level & full chip level
• Develop scripts based utilities and support verification activities
• Senior Verification engineer needs to closely work with ASIC/SoC architects in defining and developing the verification environment
• Meeting project milestone deadlines and adhere to sign-off Quality guidelines
• Expertise in debugging complex verification issues
• Understanding of hierarchical planning (top down and bottom up) and integration.
• Mentor and guide the team of Design Engineers
Required Skillset
• Develop block and system-level test benches and verification environments using Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and/or other verification languages as appropriate.
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
• Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification.
• Good understanding of ARM processor architecture is plus.
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Good team player with excellent communication skills, interfacing with the RTL Design team / Architects
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, and Ethernet etc
• Must have participated in multiple successful releases of verification modules
c)Job Code : ASIC/SoC-VER03
Designation : Team Lead – Verification
Experience : 6-10 years
Qualification : B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed Verification requirements, Environment, Test Bench development and conduct design reviews
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
Required Skillset
• Proven experience of the design verification methodologies such as Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and assertion based coverage driven verification (code & functional coverage), constraint random test generation
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage.
• Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC
• Must have good understanding about different modelling schemes – TLM, behavior/abstract level, cycle accurate, etc
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification.
• Good understanding of ARM & other processor architecture
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, DDR2/3 controller, SATA controller and NAND flash controller and Ethernet etc
• Must have participated in multiple successful releases of verification deliverables
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Good team player with excellent communication skills, interfacing with the RTL Design team / Architects
d)Job Code : ASIC/SoC-VER04
Designation : Manager – Verification
Experience : 10+ years
Qualification : B.Tech/MTech in Electrical /Electronics /Computer Science Engineering
Job Description
• Primary driver involving feasibility study, specs finalization, project proposal, project management and execution
• Developing detailed Verification requirements, Environment, Test Bench development and conduct design reviews
• Envision, build and lead a team for successful project execution
• Adhere to Project Schedule, Work Assignments and Quality processes
• Evaluate new methodology and process improvements to achieve higher efficiency and performance of the team
• Strong Customer interface for negotiating specs, design reviews till final sign off
• Mentor and Guide Junior & Senior members of the team
• The candidate to work with cross functional teams for system level solution
• Support in the business development, strategy planning
Required Skillset
• Proven experience of the design verification methodologies such as Verilog / SystemVerilog, C/C++, SystemC, VMM/ OVM/ UVM and assertion based coverage driven verification (code & functional coverage), constraint random test generation
• Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage for complex ASIC / SoC designs
• Must have good understanding of embedded processor based SoC architecture and must have completed verification of one or more embedded processor based SoC
• Must have good understanding about different modelling schemes – TLM, behavior/abstract level, cycle accurate, etc
• Must be knowledgeable on ASIC verification methodologies and levels – functional, RTL, gate level, timing, etc., DFT and BIST and processor verification.
• Good understanding of ARM & other processor architecture
• Must have conducted functional simulations, exposure to functional coverage and bug management schemes
• Knowledge of scripting Language with PERL, TCL, AWK, shell scripting.
• Protocol Knowledge on PCI, PCIe, USB2.0/3.0, DDR2/3 controller, SATA controller and NAND flash controller and Ethernet etc
• Must have participated in multiple successful releases of verification modules
• Full understanding of hierarchical design planning (top down and bottom up) and integration
• Good team player with excellent communication skills
• Strong technical leadership and people management skills
1. AMS Circuit Design Engineers:
(Data Converters, Power Management, Serial Interfaces and PLLs)
2. AMS Custom Layout Design Engineers:
(Data Converters, Power Management, Serial Interfaces, PLLs and RF)
3. Library Development Circuit Design & Characterisation Engineers:
(Standard Cell, IOs and Memory)
4. Library Development Layout Design Engineers:
(Standard Cell, IOs and Memory)
5. Physical Design Engineers :
(Digital / Mixed Signal ASIC / SoC Design)
6. Verification Engineers :
(Digital / Mixed Signal ASIC / SoC Verification)